Speculation on future FPGA development

For the development of FPGA technology, the acquisition of Xilinx and alter by amd and Intel respectively is obviously a major turning point in this story. With the change of the FPGA company from an independent company to a sub-department of the chip giant, its technology development strategy will also change greatly. This document will make a perspective for the development of this strategy.

First of all, with the integration with chip giants, FPGA will be further integrated with traditional chips to fully exploit its programmable advantages to enable new capabilities of traditional chips and even create new categories of chips.

New types of FPGA-enabled chips

For Intel, an example of this new category of chips is the IPU (Infrastructure Processing Unit). With the extensive use of the data center, some important tasks in the data center, including network control, storage management, and network security, also have increasing demands on processing power. With major chip companies launching their own solutions, Intel has also launched IPUs for this market. Last month, Intel has just published its roadmap for the future of the IPU, in which we see that the IPU in the future until 2026 will include two versions, one is a high-performance ASIC-based version and the other is a high-performance version. FPGA-based programmable version (including Oak Springs Canyon in 2022, Hot Springs Canyon in 2023/2024, and planned version in 2025/2026). Among them, the IPU based on the FPGA version is actually an acceleration card that integrates the Intel FPGA chip and Intel Xeon CPU. It can handle various network, storage, and security protocols flexibly, to ensure maximum programmability without worrying about compatibility.

In fact, for FPGA solutions similar to data center storage and networking, there have been startups involved in related projects in recent years. However, with the admission of the giant Intel, we believe that such fpga+cpu solutions will really become one of the main solutions. The fact that start-ups get involved in relevant projects and obtain financing shows that technical direction is feasible, and Intel’s entry into this market has brought green resources that start-ups do not have. We believe that in the coming years, FPGA and CPU will be more closely integrated (eg chiplet), to truly make the flexible and programmable IPU a new category of FPGA-enabled chip.

Coincidentally, amd is also actively planning to integrate by Xilinx FPGA and AMD CPU – in AMD earnings call in May, CEO Lisa Su announced that it would launch a CPU embedded with the Xilinx AI engine in 2023, that is, a CPU with powerful AI computing power. Until now, AI-related computing has been done on GPUs or other dedicated acceleration hardware. Intel’s past efforts to optimize AI running on the CPU have not been widely recognized by the market, as long as the number of CPU computing units is limited. However, since the overall AI task is not only a neural network, but also other parts of the program execution running on the CPU, if the CPU and the AI ​​acceleration unit can be closely coupled, the performance will be improved. overall task performance. It is also believed that this is the original intention of amd to propose a CPU integrated with the FPGA AI engine, and this is also an example of a new category of chips enabled by FPGA.

In short, with the increased popularization of tasks such as data centers and artificial intelligence, giants such as Intel and amd will consider how to make full use of FPGA flexibility to address these markets. In the current situation, it is not the best solution to launch FPGA products, but to launch new chip categories by integrating FPGA and other chips, which will be an important market direction for FPGA in the future. Next, we will also forecast the most critical breakthrough point of FPGA in the future from the technical direction.

Greater integration and connectivity

As mentioned above, since FPGAs are to play a key role in enabling new chip systems, we believe that integration and interconnection has become an important technical hotspot. The integration and interconnection here include two levels: first, at the FPGA level, we believe that the FPGA chip itself will integrate more and more related IPS, so that the FPGA chip is more functional and efficient; The other level is the integration of FPGA and other chips in the system. We believe that chipet and other advanced packaging technologies and related interconnection technologies will be at the core.

First of all, at the FPGA chip level, FPGA provides flexibility, but is inefficient for general modules (such as processors). Therefore, the integration of hard IP on the FPGA chip to meet the requirements of efficiency and flexibility will remain the main idea, and the number of integrated IP will be more and more in the future. On the same chip, FPGA is used as the core module, and other hard IP modules (such as CPU, Ethernet, video codec, and memory control) are carried at the same time. NOC and other on-chip interconnect schemes are used to connect FPGAs and other IPS. Amd/xilinx is a pioneer in this field. It can be seen from the versal product wiring diagram that more and more hard IP will be integrated into the chip, and Intel’s FPGA will have a similar design in this regard. By integrating these hard IPS, FPGA will be able to provide more functions. For Xilinx, the most critical IP is AI-related DSP, and we have also seen some new IP, such as direct RF, which can directly support RF applications through ultra-high-speed digital-to-analog conversion, and is expected to be combined with FPGA to meet various wireless communication requirements. In this way, a real software radio can be realized, thus opening up new application scenarios for FPGAs. Therefore, the integration of more and more hard IP into the FPGA chip will become an important technical path to further strengthen the FPGA function and enter new application scenarios.

The second level is the integration and interconnection of FPGAs and other chips at the system level. We believe that such integration will be the key for FPGAs to enable new chip categories and systems. Combined with the harder IP integration in the FPGA chips mentioned above, we believe that FPGAs with more and more powerful functions can enable more and more categories of new chips and open up the market. At this level, we believe that the most critical technology path is flexible and customizable heterogeneous integration in the form of advanced packaging, complemented by innovative interconnection technologies. In this regard, Intel previously launched the use of advanced packaging technology (emib) to integrate FPGA, high-speed transceiver (for data center scalability interconnect), and DRAM in a single package. At the hotchips conference later this year, Intel also presented a report on using heterogeneous integration to realize innovative RF applications. The main advantage of heterogeneous integration lies in its flexibility. For example, it can be integrated with different types and specifications of chips according to the needs of users, to maximize the balance between performance, cost and customization.

Similarly, amd plans to integrate Xilinx FGPA and CPU. Although no specific technical parameters have been released at present, we believe that chiplet technology can also be used in accordance with AMD prior investment in chipet and AMD previous relevant patents.

As the scale of such integration becomes larger and larger, the demand for interconnection becomes higher and higher. Otherwise, interconnection can become a bottleneck in multichip systems. The interconnect must not only provide high bandwidth, but also support important system-level functions such as caching and memory consistency. Currently, both Intel and AMD FPGAs support the relevant CXL protocol. We believe that with larger-scale integration between FPGAs, processors, and other chips, increasingly complex and high-speed interconnection between chips will become a key technology.

Software will be key

In addition to hardware, how to make the most efficient use of FPGAs in practical tasks is also an extremely critical issue. Since the FPGA and other chips (such as the CPU) are tightly integrated to form a heterogeneous chip system, how to ensure that software can make full use of the FPGA and avoid programming bottlenecks is a very complex but important. This is a very challenging problem, because the programming model of the FPGA and other parts of the system (such as the CPU) can be very different. So how to ensure that the software can partition tasks correctly (i.e. assign tasks suitable for FPGAs to FPGAs and tasks suitable for other processors to corresponding processors), reasonably handle scheduling and memory management, and provide a way easy to use for software engineers, it’s a great project. These tasks are quite different from the traditional ones. fpga-software (i.e. mainly for front-end and back-end logic synthesis tasks).

In this field, Intel and amd they are actively investing. For example, in Intel’s published IPU roadmap, open and flexible software ecology is a major investment area for Intel. Consequently, Intel has just announced that it will acquire Codeplay, a cross-platform heterogeneous chip software compiler. This move is also seen by the industry as an investment in the next generation. fpga-software. At the same time, amd also said at the financial reporting conference in May that it would invest vigorously in the software field, which obviously also includes FPGA-related software research and development. We believe that as FPGAs become an important part of the new chip system, the corresponding software ecology must also be maintained, for this new FPGA system paradigm to truly enter the mainstream.

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